1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to doping methods for fully-depleted SOI structures, and a device comprising the resulting doped regions.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
As transistors are continually scaled in keeping with the requirements of advancing technology, device reliability dictates a concomitant reduction in the power supply voltage. Hence, every successive technology generation is often accompanied by a reduction in the operating voltage of the transistor. It is known that transistor devices fabricated on silicon-on-insulator (SOI) substrates exhibit better performance at low operating voltages than do transistors of similar dimensions fabricated in bulk silicon substrates. The superior performance of SOI devices at low operating voltage is related to the relatively lower junction capacitances obtained on an SOI device compared to a bulk silicon device of similar dimensions. The buried oxide layer in an SOI device separates active transistor regions from the bulk silicon substrate, thus reducing junction capacitance.
FIG. 1 depicts an example of a transistor 10 fabricated on an illustrative silicon-on-insulator substrate 11. As shown therein, the SOI substrate 11 is comprised of a bulk substrate 11A, a buried oxide layer 11B, and an active layer 11C. The transistor 10 is comprised of a gate insulation layer 14, a gate electrode 16, sidewall spacers 19, a drain region 18A, and a source region 18B. A plurality of trench isolation regions 17 are formed in the active layer 11C. Also depicted in FIG. 1 are a plurality of conductive contacts 20 formed in a layer of insulating material 21. The conductive contacts 20 provide electrical connection to the drain and source regions 18A, 18B. As constructed, the transistor 10 defines a channel region 12 in the active layer 11C beneath the gate insulating layer 14. The bulk substrate 11A is normally doped with an appropriate dopant material, i.e., a P-type dopant such as boron or boron difluoride for NMOS devices, or an N-type dopant such as arsenic or phosphorous for PMOS devices. Typically, the bulk substrate 11A will have a doping concentration level on the order of approximately 1015 ions/cm3. The buried oxide layer 11B may be comprised of silicon dioxide, and it may have a thickness of approximately 200-360 nm (2000-3600 xc3x85). The active layer 11C may be comprised of a doped silicon, and it may have a thickness of approximately 5-30 nm (50-300 xc3x85).
Transistors fabricated in SOI substrates offer several performance advantages over transistors fabricated in bulk silicon substrates. For example, complementary-metal-oxide-semiconductor (CMOS) devices fabricated in SOI substrates are less prone to disabling capacitive coupling, known as latch-up. In addition, transistors fabricated in SOI substrates, in general, have large drive currents and high transconductance values. Also, the sub-micron SOI transistors have improved immunity to short-channel effects when compared with bulk transistors fabricated to similar dimensions.
Although SOI devices offer performance advantages over bulk silicon devices of similar dimensions, SOI devices share certain performance problems common to all thin-film transistors. For example, the active elements of an SOI transistor are fabricated in the thin-film active layer 11C. Scaling of thin-film transistors to smaller dimensions requires that the thickness of the active layer 11C be reduced. However, as the thickness of the active layer 11C is reduced, the electrical resistance of the active layer 11C correspondingly increases. This can have a negative impact on transistor performance because the fabrication of transistor elements in a conductive body having a high electrical resistance reduces the drive current of the transistor 10. Moreover, as the thickness of the active layer 11C of an SOI device continues to decrease, variations in the threshold voltage (VT) of the device occur. In short, as the thickness of the active layer 11C decreases, the threshold voltage of the device becomes unstable. As a result, use of such unstable devices in modern integrated circuit devices, e.g., microprocessors, memory devices, logic devices, etc., becomes very difficult if not impossible.
Additionally, off-state leakage currents are always of concern in integrated circuit design, since such currents tend to, among other things, increase power consumption. Such increased power consumption is particularly undesirable in many modern consumer devices employing integrated circuits, e.g., portable computers. Lastly, as device dimensions continue to decrease in fully depleted SOI structures, increased short channel effects may occur. That is, in such fully depleted devices, at least some of the field lines of the electric field of the drain 18A tend to couple to the channel region 12 of the transistor 10 through the relatively thick (200-360 nm) buried oxide layer 11B. In some cases, the electric field of the drain 18A may act to, in effect, turn on the transistor 10. Theoretically, such problems may be reduced by reducing the thickness of the buried oxide layer 11B and/or increasing the doping concentration of the bulk substrate 11A. However, such actions, if taken, would tend to increase the junction capacitance between the drain and source regions 18A, 18B and the bulk substrate 11A, thereby negating one of the primary benefits of SOI technology, i.e., reducing such junction capacitance.
The present invention is directed to a device and various methods that may solve, or at least reduce, some or all of the aforementioned problems.
The present invention is generally directed to doping methods for fully-depleted SOI structures, and a device comprising such resulting doped regions. In one illustrative embodiment, the device comprises a transistor formed above a silicon-on-insulator substrate comprised of a bulk substrate, a buried oxide layer and an active layer, the transistor being comprised of a gate electrode, the bulk substrate being doped with a dopant material at a first concentration level. The device further comprises a first doped region formed in the bulk substrate, the first doped region being comprised of a dopant material that is the same type as the bulk substrate dopant material and having a greater concentration level of dopant material than the first concentration level of the bulk substrate, the first doped region being substantially aligned with the gate electrode.
In another illustrative embodiment, the device comprises a transistor formed above a silicon-on-insulator substrate comprised of a bulk substrate, a buried oxide layer and an active layer, the transistor being comprised of a gate electrode, the bulk substrate being doped with a dopant material at a first concentration level. The device further comprises first, second and third doped regions formed in the bulk substrate, the first, second and third regions being comprised of a dopant material that is the same type as the bulk substrate dopant material, the first, second and third regions having a greater concentration level of dopant material than the first concentration level of the bulk substrate, the first doped region being substantially aligned with the gate electrode and vertically spaced apart from the second and third doped regions.
In one illustrative embodiment, the method comprises forming a gate electrode above a silicon-on-insulator substrate comprised of a bulk substrate, a buried oxide layer and an active layer, the bulk substrate being doped with a dopant material at a first concentration level. The method further comprises performing an ion implant process using at least the gate electrode as a mask to implant a dopant material into the bulk substrate, the implant process being performed with a dopant material that is of the same type as the dopant material in the substrate, the implant process resulting in a first doped region formed in the bulk substrate that is substantially self-aligned with the gate electrode, the first doped region having a dopant concentration level that is greater than the first dopant concentration level of the bulk substrate.
In yet another illustrative embodiment, the method comprises forming a gate electrode above a silicon-on-insulator substrate comprised of a bulk substrate, a buried oxide layer and an active layer, the bulk substrate being doped with a dopant material at a first concentration level, and performing an ion implant process using at least the gate electrode as a mask to implant a dopant material into the bulk substrate, the implant process being performed with a dopant material that is of the same type as the dopant material in the bulk substrate, the implant process resulting in first, second and third doped regions formed in the bulk substrate, the first doped region being substantially self-aligned with the gate electrode and vertically spaced apart from said second and third doped regions, the first, second and third doped regions having a dopant concentration level that is greater than the first dopant concentration level of the bulk substrate.